DK-DEV-5SGXEA7N【PDF 94/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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4-24

Fractional PLL Architecture

SV51005

2014.01.10

Table 4-6: Location of Middle PLLs for PLL Migration

Variant

Member Code

Left Side

Middle PLL Location

Right Side

A5

A7

A9

FRACTIONALPLL_X0_Y53 ,

FRACTIONALPLL_X0_Y66

FRACTIONALPLL_X210_Y53 ,

FRACTIONALPLL_X210_Y66

Stratix V GX

AB

B9

FRACTIONALPLL_X0_Y77 ,

FRACTIONALPLL_X0_Y86

FRACTIONALPLL_X225_Y77 ,

FRACTIONALPLL_X225_Y86

BB

D6

D8

FRACTIONALPLL_X0_Y65 ,

FRACTIONALPLL_X0_Y78

FRACTIONALPLL_X208_Y65 ,

FRACTIONALPLL_X208_Y78

Related Information

PLL Locations in Stratix V Devices on page 4-17

Provides more information about CLKIN pin connectivity to the middle PLLs.

Fractional PLL Architecture

Figure 4-24: Fractional PLL High-Level Block Diagram for Stratix V Devices

To DPA Block

For single-ended clock inputs, only the CLK<#>p pin

has a dedicated connection to the PLL. If you use the

CLK<#>n pin, a global or regional clock is used.

pfdena

Lock

Circuit

locked

÷2, ÷4

÷C0

Casade Output

to Adjacent PLL

GCLKs

Dedicated

Clock Inputs

4

inclk0

Clock

÷N

clkswitch

PFD

CP

LF

VCO

8

÷2

8

8

÷C1

÷C2

RCLKs

External Clock Outputs

GCLK/RCLK

inclk1 Switchover

Block

clkbad0

clkbad1

VCO Post Divider

÷C3

TX Serial Clock

Only C0, C2, C15, and C17

can drive the TX serial clock

Cascade Input

from Adjacent PLL

activeclock

TX Load Enable

FBOUT

and C1, C3, C14, and C16

can drive the TX load enable.

This FBOUT port is fed by

the M counter in the PLLs.

Dedicated refclk

Delta Sigma

Modulator

÷C17

÷M

Direct Compensation Mode

ZDB, External Feedback Modes

LVDS Compensation Mode

Source Synchronous, Normal Modes

External Memory

Interface DLL

PMA Clocks

FBIN

DIFFIOCLK Network

GCLK/RCLK Network

Fractional PLL Usage

You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode.

One fractional PLL can use up to 18 output counters and all external clock outputs. Two adjacent fractional

PLLs share the 18 output counters.

Fractional PLLs can be used as follows:

? Reduce the number of required oscillators on the board

Altera Corporation

Clock Networks and PLLs in Stratix V Devices

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